Conventionally, a circuit 100 such as shown in FIG. 1 is used for data transmission to memory modules 110. The circuit 100 comprises a transmission path 115 from a driver 120 to the several memory modules 110. The memory modules 110 may be, for example, dual inline memory modules (DIMMs). The memory itself may be, for example, double data rate (DDR) synchronous dynamic random access memory (SDRAM). The transmission line 115 has a series resistance 125 between the driver 120 and the memory modules 10 to dampen reflections coming back from the memory modules 110. The reflections are due to impedance mismatches between the transmission line 115 and the memory modules 110 and detrimentally interfere with signal transmission. The circuit 100 has a parallel resistance 130 that is on the opposite side of the memory modules 110 as the series resistance 125. The parallel resistance 130 matches the impedance of the transmission line 115 such that there will be no reflections back from the end of the transmission line 115. Thus, the parallel resistor 130 serves to terminate the signal at the end of the transmission line 115. The parallel resistance 130 is coupled to a termination voltage 140.
The circuit of FIG. 1 is adequate for many types of memory modules. However, the need for ever more memory has led to memory modules for which the conventional circuit of FIG. 1 is inadequate. For example, in order to get more memory on a memory module, some memory modules are “double high”. For example, a second DRAM may be incorporated onto each memory module. Unfortunately, “double high” configurations can cause increased signal reflection if the conventional circuit of FIG. 1 is used. For example, a portion of the signal transmitted to the memory modules reflects back towards the buffer. Such signal reflections degrade the signal considerably.
FIG. 2 is a graph 200 of voltage versus time illustrating an exemplary signal 210 transmitted on the transmission line 115 of the circuit 100 of FIG. 1. The exemplary signal 210 exhibits considerable degradation due to reflections. The exemplary signal 210 ideally would appear as a square wave (not depicted) and should fall continuously to its minimum and then rise continuously. However, reflections on the transmission line cause the exemplary signal 210 to have a non-monotonic region 215a on the generally falling edge. The non-monotonic region 215a on the falling edge has a portion that increases in magnitude slightly. Further, the reflections can also cause non-monotonic region 215b on the generally rising edge that has a portion that decreases in magnitude slightly. These non-monotonic regions 215a, 215b can interfere with proper registering of the data, especially in a source synchronous system. For example, a source synchronous system typically comprises a strobe trace for each eight data traces. A signal is sent on the strobe trace at the same time as signals arc sent on the data traces in order to instruct the memory modules to clock in the data on, for example, the rising edge of the strobe signal. However, if the signal on the strobe trace is distorted, such as depicted in FIG. 2, the timing for clocking in the data can be thrown off such that the data is not properly registered. For example, a false rising edge may be detected, and consequently the data may be registered at the wrong point in time.
Thus, one problem with some conventional circuits for delivering a signal to or from a memory module is that memory units added to the memory module cause problematic signal reflection that degrade signal quality. Another problem with some conventional circuits for delivering a signal to or from a memory module is that data maybe improperly registered if the circuit is used to access a memory configuration with added memory modules.